Dynamic random-access memory (DRAM) chips contain many other transistors besides the access transistor to enable full operation of the DRAM memory.
These peripheral transistors must meet stringent requirements which preclude a ‘copy-paste’ of regular logic transistor process flows.
One critical requirement imposed by present DRAM chip architectures is the ability of the periphery to withstand thermal treatments at 550-600°C and above.
Imec began its quest for thermally stable DRAM peripheral transistors in 2007. Read about this journey in EDN (in two parts) and learn more about:
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DRAM periphery basics (EDN, part 1)
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imec’s platform for thermally stable DRAM peripheral transistors – from planar high-k/metal-gate transistors to FinFETs (EDN, part 2)
Alessio Spessot received an M.Sc. degree in Physics (magna cum laude) from Trieste University in 2003 and a Ph.D. degree in Solid-State Physics from the Modena University in 2006. He has worked for STMicroelectronics, Numonyx, and Micron, where he was involved in developing advanced CMOS, DRAM, NAND, emerging memory array, and periphery. Since 2016, he has been with imec, where he is currently Technical Account Director.
Naoto Horiguchi is the Director of CMOS Device Technology at imec. He obtained a degree in Applied Physics in 1992 from the Tokyo University, Japan. He has worked in Fujitsu and the University of California Santa Barbara, where he was involved in developing devices using semiconductor nanostructures and advanced CMOS. He has been with imec since 2006, where he is engaged in advanced CMOS device R&D together with worldwide industrial partners, universities, and research institutes. His current focus is on CMOS device scaling down to the 1nm technology node and beyond.
Published on:
6 March 2025
