Extending RISC-V Instruction Generation for Custom SIMT Cores

RISC-V Random Instruction Sequence (RIS) generation tools are essential for testing and validating RISC-V processors by generating random sequences of instructions that simulate various operational scenarios. These tools help ensure the robustness, performance, and correctness of the processor's implementation by uncovering potential bugs and verifying compliance with the RISC-V specification. 

The objectives of this internship would be:

• Study and evaluate existing RISC-V random instruction sequence generation tools.
• Develop integration solutions to seamlessly incorporate these tools into our in-house modeling frameworks.
• Extend the RISC-V tools to support our custom instructions.
• Study and Implement compatibility features for Single Instruction, Multiple Threads (SIMT) cores.

By integrating these tools with in-house modeling frameworks and extending them to support custom instructions and SIMT core compatibility, we can enhance our testing capabilities and ensure that our custom processors meet the highest standards of reliability and performance.
 

Language requirements: English 

Type of Project: Internship 

Bachelor's program/required background: Computer Science, Computer Architecture 

Mentor: Jonas Svedas 

For more information or application, please contact Jonas Svedas (jonas.svedas@imec-int.com)