User-Friendly 3D-CoSTAR

The market continues to pull for integrated-circuits (ICs) with higher performance, better energy-efficiency, and lower cost. While conventional transistor scaling runs into increasing technical and financial hurdles, the baton in the race to create attractive new IC products that meet market expectations is gradually being taken over by innovations in multi-die stack-assembly and packaging techniques. Large-array fine-pitch micro-bumps implement dense high-performance low-power inter-die interconnects. Through-silicon vias (TSVs) in combination with wafer thinning provide electrical connections via the backside of a die’s substrate, enabling stacks of more than two dies. Packaging costs are drastically reduced by using cheaper materials and wafer-level processes. The I/O-to-pin fan-out functionality of package substrates is replaced by redistribution metal layers, cost-effectively manufactured at wafer level. And the cost of (often expensive) plastic or ceramic packages is circumvented by applying epoxy mould compounds at wafer level. These and other interconnect, assembly, and packaging technology innovations lead to a wide range of multi-die stack architectures, including Package-on-Package (PoP), 2.5D-stacked ICs (SICs) consisting of multiple active dies stacked side-by-side on a passive silicon interposer base, 3D-SICs comprising one or multiple towers of stacked active dies, flip-chip fan-out wafer-level packages (FC-FOWLP), etc. Both in product variety and volumes we have yet only seen the beginning of multi-die stacks.
 
Like all micro-electronic products, multi-die stacks need to be tested for manufacturing defects before they can be shipped with acceptable quality levels to their customers. We distinguish the following tests: (1) pre-bond tests prior to stacking, (2) mid-bond tests on incomplete, partial stacks, (3) post-bond tests on complete yet still not packaged stacks, and (4) final tests on the final packaged product. The number of possible test flows grows quickly with the number of dies in the stack and hence is the subject of automated trade-off evaluation and optimization. Together with the Technical University of Delft (TUD), we have built a prototype software tool, 3D-CoSTAR, which can make these trade-offs. However, 3D-CoSTAR’s interface (both on the input and output side) is not very user-friendly, which is an obstacle for usage by semiconductor companies.
 
This student project entails building a user-friendly version of 3D-CoSTAR. This can be done by generating a user-friendly shell around 3D-CoSTAR as core or by implementing a new version of 3D-CoSTAR from scratch. You will first be made familiar with the current 3D-CoSTAR version and its calculations. Then, we will ask you to prepare and present a plan for a user-friendly version of that tool. After you have obtained green light for your plan, you will also be the main person implementing it – of course under supervision of professional software developers like Dieter Claes.
 
For this application we envision a user-friendly command line interface (CLI), passing information to a well thought out internal data model on which the multi-step cost simulation is performed after which the selected results are provided to the user in a clear and convenient format. A possible extension of this would be the inclusion of a graphical user interface (GUI) to further improve the user experience and ease of adoption. Finally, but not less important, is clear documentation, usage guidelines, and examples/tutorials. It is likely (but not fixed yet) that these will be built in Python(3), with the GUI build in the QT framework, as this would allow you to build on pre-existing (imec) libraries and expertise.
 
We are looking for a student Computer Science / Informatics, with high/excellent grades and an interest to learn something regarding the manufacturing and test of integrated circuits (ICs). You should have experience writing Python applications in accordance to PEP guidelines, should be familiar with object-oriented programming, and pyQT GUI development. Deep knowledge of semiconductors is not required, but good mastering of the English language is, given the fact that imec is a very international place and English is the default language. Location: at imec’s headquarters in Leuven, Belgium. Duration of the project: 9 months. Start: to be decided, Sept/Oct 2024 at earliest.

 
What do we offer:

• An interesting and relevant project for nine months, which, if successful, will have real application in the industry.
• Supervision by Erik Jan Marinissen (worldwide-recognized “IC test” expert, has supervised 50+ students) and Dieter Claes (professional software developer in a semiconductor context, has supervised 15+ students).
• A flex desk working space.
• A notebook PC during the entire project.
• A remuneration of EUR 1000/month gross.

You can do this project as an internship, in which you gain experience how it is to work in a research environment like imec. However, if your university agrees, then this project might also serve as your MSc graduation (“thesis”) project.
 
Supervisors:

Dieter Claes (https://www.linkedin.com/in/dieter-claes/)
Erik Jan Marinissen (https://www.linkedin.com/in/erikjanmarinissen/)

Type of Project: Internship; Thesis; Combination of internship and thesis 

Master's degree: Master of Engineering Technology; Master of Science 

Master program: Computer Science; Nanoscience & Nanotechnology; Other

Duration: ~9 months 

For more information or application, please contact Dieter Claes (dieter.claes@imec.be)

Imec allowance will be provided.