PDK development strategies for advanced technologies

As we continue to evolve our CMOS/Memory Technology devices to cater to the growing need for higher functionality per chip, the complexity of design enablement process has increased manyfold.  Thus, we are in dire need to come up with different strategies and methodologies to ease the design enablement process. This process involves generation of reliable PDKs consisting electrical behavior of the device and, physical guidelines of the underlying technology for purpose of design.

Technology exploration often requires generation of specialized PDKs for both novel and state of the art technologies for faster technology evaluation. However, the generation of design enablers manually is complex and error prone. The development of systematic and automated processes for generation of these enablers reduces the challenges and provides additional flexibility for the designers.

This project targets to explore the state-of-the-art technologies (beyond 2 nm CMOS nodes) and develop an automated framework for the advanced PDKs. The goal is to generate reliable and quality assured PDKs with minimal manual intervention. DRC deck review, coding in several languages, schematic-layout creation, and PDK testing will be a part of the internship.

Requirements to fulfil this project:

• Understanding of CMOS technology
• Knowledge in spice simulations.
• Familiarity with Cadence Virtuoso (schematic, layout), Siemens Calibre DRC-LVS is a plus.
• Strong programming skills in Python, Perl, shell
• Knowledge of SKILL and Tcl is a plus
• Knowledge of Linux
• Communicative and active team player