Error sensitivity of Design Technology Co-Optimization (DTCO) flows in advanced CMOS nodes

Introduction & context 

Imec's Pathfinding of Semiconductor Technologies Department is performing R&D activities on the near-future CMOS process nodes, covering up to several nodes beyond today's cutting-edge commercially available N3 FinFET node. We are focusing on the implications of those future CMOS device architectures (e.g. nanosheet, CFET, 2D FET) from modeling to the block-level (e.g. processor, multi-core, 3D). We are pathfinding for future technology enablers by Design Technology Co-Optimization (DTCO) and System Technology Co-Optimization (STCO) cycles. 
As the CMOS scaling further continues, the error margins in the FEOL (device) and BEOL (interconnect) modelling and timing/power library characterization flows that build our DTCO flow get thinner. As a result, we must create a clear map of the error sensitivities that exist in the current flows. This error mapping task is technology-dependent, and this dependency will be at the core of the expected output. 

Your main responsibilities 

In this MSc thesis project: 

• The student will be familiarized with a large array of FEOL (device) and BEOL (interconnect) modelling, library characterization, and physical design (Synthesis, Placement and Routing) flows. 
• The most common sources of errors in the flows need to be identified. 
• For different technology nodes and different sources of errors, the student will run through the DTCO flows and determine the errors’ impact. 
• Sensitivity metrics will be evaluated at the block-level. 

Competences expected 

• Motivated, interested, analytical thinking
• Team player with effective communication skills
• Familiarity with Linux commands, device physics, digital design flow 
• Good to have a course-level of knowledge on Spectre/Spice simulations, BSIM models, parasitic RC extraction, metal-via stacks, schematic and layout editing, PnR tools (synthesis, placement and routing) 

Type of Project: Thesis; Internship 

Master's degree: Master of Science; Master of Engineering Science; Master of Engineering Technology 

Master program: Electrotechnics/Electrical Engineering 

Duration: minimum 6 months 

Supervisor: Dragomir Milojevic (ULB)

For more information or application, please contact Halil Kuekner (halil.kukner@imec.be).

Imec allowance will be provided for students studying at a non-Belgian university.