Technology-aware memory sub-system design for emerging technologies

We are in the midst of an AI-based revolution. AI-related workloads are showing up in computing devices of every scale --- TinyML, Edge AI, Cloud Analytics, etc. Consequently, an increasing focus is on designing efficient computing systems catering to specific workloads and their deployment scenario. Since data movement presents one of the primary bottlenecks to AI computing, novel memory design forms a large portion of semiconductor research. However, novel memory technologies such as Non-volatile Memories (NVMs) cannot be treated as drop-in replacements for traditional SRAM-based systems. This project focuses on exploring the workload-architecture-technology co-design space using IMEC’s technology innovations in terms of devices and system integration. The project will focus primarily on designing systems for emerging workloads such as LLMs and other generative AI applications.
 
The student will be working on a technology-aware partitioning of the memory sub-systems. The project will explore the partitioning of memory elements across system, micro-architecture, and  memory macro abstractions, to design architectures that can leverage SRAM scaling and different types of NVMs to improve both application performance and the PPA metrics of the systems.

Type of Project: Internship; Combination of internship and thesis 

Master's degree: Master of Engineering Technology; Master of Engineering Science 

Master program: Computer Science; Electrotechnics/Electrical Engineering 

Duration: 6 months 

For more information or application, please contact Siva Satyendra Sahoo (siva.satyendra.sahoo@imec.be).

Imec allowance will be provided for students studying at a non-Belgian university.