Enabling workload-driven novel system-level reconfiguration methods leveraging system technology co-optimisation.

With the increasing diversity of domains using AI/ML-based applications, there is a growing diversity of workload requirements from electronic systems. While heterogeneous computing systems (CPU, GPU, and NPU accelerators) provide some level of optimization, the static nature of computation, communication, and memory elements limits the level of utilization for emerging workloads. Similarly, state-of-the-art reconfigurable systems (FPGAs, CGRAs, etc.) focus on runtime reconfiguration targeted at functionality modifications only.
 
The student will be working on a workload-aware system-level exploration framework. The project will involve identifying system-level designs that can leverage existing reconfigurable technologies, across computation, communication, and memory, to provide optimized PPAC (power, performance, area, and cost) trade-offs for a set of workloads. The project will focus more on the memory aspects of FPGA-based systems.

Type of Project: Internship; Combination of internship and thesis 

Master's degree: Master of Engineering Technology; Master of Engineering Science 

Master program: Computer Science; Electrotechnics/Electrical Engineering 

Duration: 3-6 months 

For more information or application, please contact Siva Satyendra Sahoo (siva.satyendra.sahoo@imec.be).

 Imec allowance will be provided for students studying at a non-Belgian university.