Open-Source Physical Design Flow Development for Advanced CMOS Nodes

Project description: 
 
In Physical Design Research (PDRS) team, we explore the future of CMOS device architectures (e.g., nanosheet, CFET, 2D FET) by conducting block-level physical design research (e.g., multi-core, 3D). Our missions are identifying future technology enablers and pathfinding for future technology development through Design Technology Co-Optimization (DTCO) and System Technology Co-Optimization (STCO) cycles.

We are seeking a motivated master's student to join our project focused on developing a physical design flow using open-source EDA tools for advanced CMOS nodes of 2nm and below. As advanced semiconductor technology and commercial EDA tools become increasingly restrictive and costly, there is a pressing need for the academic community to have affordable and easy access to cutting-edge design flows. This accessibility is crucial for driving research in chip design for advanced technologies. Additionally, novel physical design features, such as back-side power down network (BSPDN), emerge with the development in advanced technology. Open-source design flows could offer a flexible and rapid implementation platform for exploring these innovative design ideas.

Project Objectives:

In this project, you will collaborate with the researchers of the Physical Design Research (PDRS) team to enhance the open-source place & route (P&R) flow, supporting imec's first design pathfinding process design kit for N2 node (N2-PDK). The flow could facilitate early evaluation of the performance-power-area-cost (PPAC) impact of novel physical design features (e.g., BSPDN) on digital designs, and facilitate novel design and architecture research on imec's N2 pathfinding process.
 
Project Tasks:

• Understand the latest developments in cutting-edge CMOS technology nodes of 2nm and below.
• Learn to use state-of-the-art digital design flows (synthesis, P&R) with both commercial and open-source EDA tools to implement chip designs with millions of logic gates.
• Work with the PDRS team to enhance the open-source P&R flow to enable digital designs using N2-PDK
• Conduct physical design experiments (synthesis, P&R) to research the impact of scaling boosters (e.g., BSPDN) on the PPAC of designs.

Requirements to fulfil this project:
 

• Understanding of CMOS technology
• Understanding of digital circuit design flow (synthesis, P&R)
• Knowledge of Linux 
• Communicative and active team player
• Programming skill in Python, Tcl, shell is a plus
• •    Prior experience with EDA tools is a plus

Further Readling:

• Imec launches the first design pathfinding process design kit for N2 node
• N2 Nanosheet Pathfinding-PDK (P-PDKTM) Including Back-Side PDN
• OpenROAD: Toward a Self-Driving, Open-Source Digital Layout Implementation Tool Chain
• Building OpenLANE: A 130nm OpenROAD-based Tapeout- Proven Flow

Type of Project: Combination of internship and thesis 

Master's degree: Master of Engineering Technology; Master of Science; Master of Engineering Science 

Master program: Electrotechnics/Electrical Engineering; Nanoscience & Nanotechnology 

Duration: 6 months 

For more information or application, please contact Ji-Yung Lin (ji-yung.lin@imec.be).

Imec allowance will be provided for students studying at a non-Belgian university.