Tackling network-on-chip (NoC) scaling challenges with a system-technology co-optimization approach

As cloud computing demands continue to grow, optimizing multi-core processors for performance, cost, and scalability is crucial. Network-on-Chip (NoC) scaling has become a bottleneck due to conflicting interconnect requirements between the dense logic and the chip communication infrastructure (the physical limits of metal interconnects).

This article examines two approaches to NoC scaling, presented in imec’s latest IEDM paper: a dedicated NoC routing die, and backside NoC signal integration. While both strategies can reduce manufacturing costs at very high bandwidths, backside integration stands out as the more scalable and cost-efficient option by co-integrating signal routes alongside the existing backside power delivery network (BSPDN).

To address the challenges of co-integrating NoC channels with the BSPDN, the researchers applied a System Technology Co-Optimization (STCO) approach. By optimizing the relationship between the BSPDN, logic layers, and NoC routing, the STCO methodology ensures that power, signal integrity, and design complexity are balanced effectively. This coordinated design framework addresses issues like IR drop, latency, and manufacturing costs, making backside integration of signal channels a promising solution for high-performance systems such as cloud server CPUs.

Read the full article, previously published in Semiconductor Digest here.