Thermal assessment and design optimization of advanced microelectronic interconnect

One of the most important parts of a microelectronic device are the nano wires that deliver power to the transistor and interconnect different logic cells allowing multi functionality to the device. These wires are called back end of line (BEOL) and they are the final stage of semiconductor processing. In today's advanced micro chip, it consists of up to fifteen layers of complex wiring. However as microelectronics continue to shrink, these wires will also be affected. By scaling metal wires, not only increases their electrical resistivity, but also significantly reduces their thermal conductivity. With the constant requirement for high power and the fact that the BEOL is embedded in a very poor thermal conductivity dielectric material, makes the interconnect highly susceptibility for self-heating at operating conditions besides to increase the thermal resistance of the electronic package. The goal of this PhD is to investigate thermal bottlenecks in BEOL and optimize interconnect design to improve thermal performance of future technology scheme.

• Thermal modeling of advanced BEOL technology node
• Assessment of scaling booster on the thermal performance of BEOL
• Evaluate high resistance thermal interfaces
• Thermal material characterization through electrical measurement
• Thermal optimization for advanced technology node
• Design thermal test structures for characterization and model validation