Power Delivery Challenges In Angstrom Nodes: Paving The Way For 3D Integrated Circuits (3D-ICs) of The Future

Semiconductor technology driven by Moore’s law has reached an inflection point due to physical and technological barriers. Further innovation is fueled by the disintegration of various functional components in an IC and subsequent re-integration using advanced packaging techniques like 2.5D and 3D system integration. The separate and more tailored optimization and integration, also popularly known as heterogeneous integration (HI) allows for achieving higher performance per Watt of power. In this context, IMEC’s CMOS 2.0 paradigm1 views separate tiers for high drive logic, high-density logic, level 1 (L1) and level 2 (L2) cache memories (SRAMs), and power delivery network (PDN), clock delivery network (CDN) and I/Os.  

However, several challenges come in the way of this attractive option: among which power delivery and thermal challenges are the foremost. Since stacking of active layers inherently implies higher power density, power supply network impedance can become prohibitively large to keep the system functional without errors. The rising power density (due to higher current per footprint) and faster transients (due to faster switching speeds) lead to higher IR and LdI/dt noise injected into the power lines respectively. With pitch scaling, the interconnect resistance has gone up significantly leading to even larger IR drops. Since the power supply impedance (considering package and board RLC) hasn’t really kept up with the scaling, the supply noise issue is critical, especially in 3D designs where the inter-layer vias (ILVs) or through Silicon vias (TSVs)  add to more parasitics. The frequency dependence of power supply impedance makes the impact sensitive to workloads.       

This PhD opportunity tries to tackle the above power delivery challenges and to propose methods, solutions and trade-off analysis for power supply noise mitigation techniques in 3D-ICs, e.g. bringing passive components such as high-density decoupling CAPs closer to the chip and enabling fully integrated voltage regulators (FIVR) for more efficient power delivery. You will work with IMEC’s advanced technology PDK suited for Angstrom nodes to lay out commercial design benchmarks executing realistic workloads. You will be using electromagnetic field simulator (e.g., High-Frequency Structure Simulator (HFSS) from ANSYS) to accurately model package and board level as well as TSV parasitics for different flavors of 2.5D and 3D integration technologies, e.g., F2F/F2B hybrid bonding. Effect of running workloads will be studied to identify noise-critical windows. Finally, you will explore opportunities to mitigate the supply noise by strategically placing decoupling capacitors/ DCAPs (e.g. on-chip 2.5D MIMCAP).  Recently, backside power delivery network (BSPDN) has been introduced to improve power integrity2 by migrating the power/ground interconnects to the back side of the wafer for more generous routing resource allocation for signals in the front side, thereby making the power lines fatter and less resistive. The backside of the wafer can be further exploited to include power switches and /or incorporating high-density MIMCAPs to filter high-frequency noise and for realizing power-efficient designs.  

More specifically, your work will involve the following activities: