Nanoscale Vacuum Channel Transistors (NVCTs) for THz communication systems
Leuven | Just now
The scaling of complementary metal–oxide–semiconductor (CMOS) field-effect transistors (FETs) has led to feature sizes of (CMOS) field-effect transistors (FETs) has led to feature sizes of <10nm. Continuing to improve the speed of these devices, while simultaneously reducing their power consumption, has become a significant challenge. To maintain progress and meet the needs of emerging markets such as the Internet of Things (IoT), autonomous vehicles and mobile applications, the semiconductor industry is considering the heterogeneous integration of different components.
Vacuum electronics, which were central to electronics before being replaced by solid-state devices, also have the potential to play an enhanced role in the future. The scalability, integration, and low power consumption advantages of solid-state electronics have been realized by continuous advances in semiconductor process technology. The miniaturization of vacuum tubes, by utilizing state-of-the-art processing technologies, can also lead to higher integration and lower operation voltage and power consumption. The vacuum state provides superior electron transport compared to all semiconductors as collisions and scattering with the crystal lattice do not occur. Thus, the electron velocity in vacuum is much higher than the saturation velocity in silicon and other high mobility semiconductors such as germanium and gallium arsenide. Driven by a combination of well-known physics and adoption of state-of-the-art integrated circuit manufacturing, vacuum channel transistors with nanoscale feature sizes can now be fabricated and presents an interesting alternative for future high-speed communications systems.
The goal of this internship is:
- To analyze the feasibility of combining heterogenous integration of different semiconductor materials to develop a high-speed and low power-loss NVCTs for more-than-THz communication systems of the future
- To provide a suitable design of such an NVCT
Type of project: Combination of internship and thesis, Internship, Thesis
Duration: 6 months
Required degree: Master of Engineering Technology, Master of Science, Master of Engineering Science
Required background: Computer Science, Electromechanical engineering, Electrotechnics/Electrical Engineering, Materials Engineering, Nanoscience & Nanotechnology, Physics
Supervising scientist(s): For further information or for application, please contact: Abhitosh Vais (Abhitosh.Vais@imec.be)
Imec allowance will be provided.