CMOS: advanced and beyond
Discover why imec is the premier R&D center for advanced logic & memory devices.
Integrated photonics
Take a look at technologies for optical transceivers, sensors and more.
Health technologies
See how imec brings the power of chip technology to the world of healthcare.
Sensing and actuation
Explore imec’s CMOS- and photonics-based sensing and actuation systems.
Connectivity technology
Look into our reliable, high-performance, low-power network technologies.
More expertises
Discover all our expertises.
Research
Be the first to reap the benefits of imec’s research by joining one of our programs or starting an exclusive bilateral collaboration.
Foundry services
Build on our expertise for the design, prototyping and low-volume manufacturing of your innovative nanotech components and products.
Venturing and startups
Kick-start your business. Launch or expand your tech company by drawing on the funds and knowhow of imec’s ecosystem of tailored venturing support.
Education and workforce development
Imec supports formal and on-the-job training for a range of careers in semiconductors.
NanoIC pilot line
Aligned with the EU Chips Act, access to the pilot line will accelerate beyond-2nm innovation.
Development of direct bonding of III-V dies to Si wafer
Master projects/internships - Leuven | More than two weeks ago
In the frame of this internship you will fully develop an advanced bonding process to enable the integration of III-V dies on Si wafers for next generations of heterogeneous integrated semiconductors.
III-V semiconductors have arisen as promising candidate for a myriad of technological developments such as: RF, optoelectronics, or photovoltaics; thanks to their unmatched opto-electronics properties. Ideally these materials would need to be co-integrated on Si to enable to use the advantages of III-V and Si on the same platform. One key development needed to enable this integration is the development of III-V dies bonding to Si. This is not as straightforward as for Si dies bonding to Si wafers due to several hurdles to be overcome. The first hurdle is the different size of III-V wafers and Si wafers which limit the process of III-V in a Si-CMOS production line. Secondly the specificiations on wafers geometry (mainly thickness tolerance) is different between these two. Finally the thermal expansion difference between III-V and Si might lead to difficulties during the post processing of the bonded dies.
In the frame of this this internship the main goal will be to developp a process which enables to overcome the different hurdles foreseen. If the first goal is reached a secondary goal focusing on the reuse of the III-V substrate to enable a more sustainable process will be explored.
In the frame of this this internship the main goal will be to developp a process which enables to overcome the different hurdles foreseen. If the first goal is reached a secondary goal focusing on the reuse of the III-V substrate to enable a more sustainable process will be explored.
Type of project: Internship
Duration: 6 months
Required degree: Master of Engineering Technology, Master of Science, Master of Engineering Science
Required background: Chemistry/Chemical Engineering, Electromechanical engineering, Energy, Materials Engineering, Nanoscience & Nanotechnology, Physics
Supervising scientist(s): For further information or for application, please contact: Francois Chancerel (Francois.Chancerel@imec.be)
Only for self-supporting students.