Design enablement and STCO for CMOS2.0 reconfigurable computing

Design enablement of multi-layer FPGA place & route environment based on existing EDA tools: while current EDA tools do offer support for 3D place & route (PnR), they do have limitations with respect to CMOS2.0 FPGA paradigm: limited number of dies when considering optimal 3D structure placement, poor scalability as the 3D interconnect pitch scales down, significant run-time for complex designs and dense 3D interconnects etc. The objective of this research is to extend the existing 3D PnR functionalities to allow implementation of technologically heterogeneous multi-die FPGAs, together with hierarchical design approach to deal with complex designs efficiently. 

Power delivery for CMOS2.0 FPGAs: assuming baseline CMOS2.0 FPGA architecture, the candidate will propose realistic 2D Power Delivery Network (PDN) architectures for each functional layer (LUT, MUX, local/global interconnect layer etc.) and decide on appropriate Die-to-Die power delivery based on imec 3D technology assumptions. Different power delivery assumptions will be quantified to allow appropriate selection depending on the architectural choices made. 

Set-up of layout-level multi-die thermal analysis and design enablement of floorplan/placement feedback loop: 3D power and thermal analysis at layout level using realistic workloads is mandatory for multi-tier designs to validate the PPA analysis, PDN architecture, stack cross-section/packaging, cooling, IR-drop and many other parameters. While such analysis could be carried out with the current state of EDA tools, there is no support to mitigate hot-spots, excessive IR-drop, etc. The candidate will propose methodologies and implement thermally aware flow specifically for CMOS2.0 FPGAs. 

PPAT benchmarking of complex designs: assuming newly proposed CMOS2.0 FPGA architecture with specific instances of LUT, MUX, local/global interconnect, configuration storage layer, etc. (cf. PhD proposals: “C2LB: Cube Configurable Logic Block for CMOS 2.0” and “Memory-based reconfigurable computing”), the candidate will work on exhaustive PPAT analysis using realistic designs from different application domains. The analysis will be carried out in an iterative approach, with the adjustments of tunable parameters to quantify PPAT holistically (e.g. adopted cooling solution vs. specific partitioning and 3D placement, 2D/3D power delivery vs. IR-drop, etc.). 

Technology co-optimization and layer FEOL/BEOL specification: in CMOS2.0 paradigm each layer could be optimized specifically for a given functionality (LUT, MUX, local/global interconnect layer, configuration storage etc.) at technology, device and standard cell levels (FEOL). Also, each interconnect layer (BEOL) could be optimized though metal pitch and Nº of metal layers deployed. The goal of this research is to analyze different technology parameters (at layer level, layer-to-layer interconnect etc.) and their impact on PPAT of CMOS2.0 FPGAs and propose the right technology knobs for a given set of representative designs.