Cost and Environmental Cost System-Technology Co-Optimization

The fundamental principle of CMOS scaling has led to dramatic improvements in computing power and performance while reducing manufacturing costs. As we are approaching limits in achievable devices and interconnect sizes, the complexity of the processes lead to increasing cost and environmental cost of fabrication. At the same time severe power, thermal, and speed roadblocks are reached at system level.

Scaling is now entering a new era of System-Technology Co-Optimization, where increasing functions per unit cost will be reached by other routes than pure dimensional scaling. System-on-a-Chips are vastly heterogeneous systems. Large advances in 2.5D and 3D technologies allow to split SoCs into multiple dies, potentially offering benefits in performance, power, cost, environmental cost. Complex memory hierarchies, multi-core, and multi-threading as well as core specialization (xPUs...) on a single system-on-chip (SoC) or in chiplets are opening a new avenue to partition systems and co-optimize them on different requirements. This can only go hand in hand with a revision of system design practices and introducing fundamentally novel architectures and devices.