Parametrized templates enabling automatic layout generation for advanced technology variations

Design-Technology Co-Optimization (DTCO) research is crucial for advanced technologies. To analyze different technology options and studying variability, we characterize different layouts, with small variations. Parametrized, automatically generated layouts, efficiently broaden the benchmarking of these variations.

In this internship, you will:

• Familiarize yourself with advanced technologies, such as nanosheet and CFET.
• Design layouts for these advanced technologies.
• Develop parametrized templates to enable automatic layout generation for variations.
• Work with and extend our inhouse software to benchmark technology variations.

During this internship you will be part of a multidisciplinary team, interacting with specialists in device physics, process integration and digital design.

By joining imec for this internship, you will become part of a world-leading research institute in nanoelectronics. At imec, we foster a collaborative culture that thrives on innovation and continuous learning. You will work within a diverse and global team of experts, where your contributions will have real-world impact. Imec supports your professional and personal development, preparing you for a future at the cutting edge of technology.

Background: Applicants should have a background in electrical engineering, nanotechnology, or related fields, with a strong cross-disciplinary interest.

Type of Project: Internship

Master's degree: Master of Engineering Science; Master of Engineering Technology

Duration: min. 3 months

For more information or application, please contact the supervising scientist Lynn Verschueren (lynn.verschueren@imec.be).

Imec allowance will be provided.