Advanced electrical characterization of novel 2D-channel pFET devices through performance, variability and reliability assessment

2D materials have been proposed for more than one decade to replace the Silicon channel in future CMOS technologies, and extend Moore’s law validity, thanks to their large electron and hole mobilities, achievable at an atomic-scale thin channel, which also provides superior electrostatic control. Their adoption by a mainstream technology, or emergence as an alternative technology to CMOS, remains however an enormously challenging task, where technological advance situates at the confluence of fundamental material understanding, innovative device engineering and process control, advanced electrical characterization and pragmatic tackling of reliability concerns and design requirements.

Despite recent advances in prototyping nFET devices, there is an acute gap in pFET pathfinding. Device research avenues are currently being explored, to control and properly access the 2D channel, by identifying potential solutions to form, encapsulate and connect the 2D material with its surrounding environment. This calls for the development of advanced device characterization techniques, to extract parameters for the channel material (e.g. mobility, subthreshold swing, threshold voltage), contact (e.g. contact resistance, M/S Schottky barrier height, access resistance), and the gate stack (e.g. EOT, defects density, doping), etc. These will allow to identify application space, through systematic benchmarking. Batch-to-batch and device-to-device variability quantification allows adding a much-needed statistical dimension to the performance benchmarking, unraveling the 2D pFET device potential, to pursue performance matching with the counterpart nFET. A first reliability assessment will complete this picture and provide insights into the device lifetime, bias-temperature instability, and will feed back to further process improvement, towards conversion of device engineering innovations into technologically viable routes.

The research work of this Ph.D. topic will be carried out at imec Leuven.

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Profile:

We are looking for an enthusiastic person with a background/MSc degree in physics, electrical engineering or materials science, to join our team and work on exploratory logic devices. Furthermore, you:

• Have hands-on experience in nanodevice characterization
• Have a solid theoretical knowledge and very good understanding of the device/2D materials physics
• Are familiar with CMOS technology, device simulation or data analysis tools, as important assets
• Are willing to publish your bes results in top-level conferences and/or high-impact journals in the field
• Are a self-driven person, able to work independently, while placing your work in the context of a larger team effort and organization’s strategic needs and priorities
• Are able to think out-of-the-box and can easily approach areas outside your comfort zone
• Can work in an interdisciplinary team, including device and process engineers, simulation and reliability experts, materials scientists; are engaged, dependable and flexible
• Have good communication, presentations and writing skills; like working in an international and multicultural environment; are fluent in English

References:

1. Z. Chang et al: How to report and benchmark emerging field-effect transistors, Nat. Electr 5(7): 416-423, 2022
2. X. Liu et al: Fermi Level Pinning Dependent 2D Semiconductor Devices: Challenges and Prospects, Adv. Mater, 34: 2108425, 2022
3. V.K. Sangwan & M.C. Hersam: Electronic Transport in two-Dimensional Materials, Annu. Rev. Phys. Chem. 69:12.1–12.27, 2018.
4. Q. Smets et al: Sources of variability in scaled MoS2 FETs, Proc. IEDM, 3.1.4, 2020
5. T.D. Ngo et al: The critical role of 2D TMD interfacial layers for pFET performance, Proc. IEDM, 2024, to appear.
6. 6. Yu. Yu. Ilarionov: Insulators for 2D nanoelectronics: the gap to bridge, Nat. Comm. 11:3385, 2020.