System technology co-optimization for high speed/high frequency chiplets and heterogeneous integration packaging

System technology co-optimization for high speed/high frequency chiplets and heterogeneous integration packaging

One of the latest advancements in semiconductor industry is the concept of chiplets, a revolutionary approach to designing and manufacturing semiconductors. Chiplets are a disruptive technology, where a monolithic chip is deconstructed into modular functional blocks or chiplets and then cleverly reassemble at the packaging level connecting the different chiplets.This LEGO-like approach marks a new era of semiconductor innovation because it promises to reduce chipmaking costs by enabling the production of different functional circuits using the most cost-effective processes.

Today, interconnects have become major bottlenecks for the chiplet concept and therefore, the improvement of interconnect speed is essential for chiplet-based system performance. However, higher speed interconnects typically also entail higher losses and therefore, system-wide optimization is required.

In this research, You'll work on the design/modelling aspects of co-optimizing chiplet-based systems for peak performance and delve into the details of heterogeneous integration technology.

Specifically, the work will entail:

• Literature review and benchmarking the state of the art.
• Minimization of the (ever increasing) number of interconnect lines between chiplets by extending interconnects to higher frequencies
• Modelling and design of high speed/high frequency interconnect with different packaging techniques
  
   
• Type of project
  Master thesis, internship
• Degree
  master’s in science and/or Master in Engineering
• Student majoring in: Electrical or Electronic Engineering, Physics, or Material Science.
• Contact person(s): For further information or for application, please contact: Xiao Sun (Xiao.Sun@imec.be)