Multi-phase Clocking of High-speed Wireline Transceivers

On the link level, the most advanced electro-optical communications between single nodes rely on multi-bit transceivers (DACs and ADCs), trading off signal resolution and bandwidth to condense as much information as possible in the available optical spectrum. This comes at the expense of significant analog and digital IC design effort, addressing on the one hand the very wideband circuit design of the interface between electrical and optical world, and on the other hand a clever adaptation and optimization based on the received data to maximize the link performance.

On top of all this, the crucial limit at the farthest end of the signal spectrum lies in the "time noise" (jitter and skew) of the synchronization and clocking among the tens of units that compose each front-end module. This is currently addressed in both industry and academia with careful co-design and optimization of the various link components (analog, "RF" and digital).

The Ph.D. candidate will explore these trade-offs by means of high-level system modelling of the wireline link (Matlab/Octave/Python/HDL...), corroborated by an in-depth analysis of  the technological limitations of the available scaled CMOS technology.

The design phase, which emphasizes the challenges of low-jitter and low-skew, multi-GHz and multi-phase clocking, will help the candidate develop crucial design skills by exploring mixed-signal feedback frequency synthesis techniques like PLLs, MDLLs and CDR-like loops.

The outcome of this Ph.D. path will be a silicon-proven, power-efficient clocking strategy for high-speed, Time-Interleaved Wireline Data Converters, targeting publications at major international conferences.