/IGZO DRAM characterization and design

IGZO DRAM characterization and design

Leuven | Just now

Understanding DRAM for bendable computational systems

Project description

In the Large-Area Thin-film Transistor Electronics (LATTE) group of imec, we design the newest generation of circuits using thin-film transistors [1, 2]. The transistor channel in these devices can be made of Indium-Gallium-Zinc Oxide (IGZO), which is deposited on flexible substrates, allowing us to make flexible circuits. We have a digital library available, allowing us to create microprocessors [3]. However, the literature is still missing a memory block to create a stand-alone system [4]. In advanced CMOS it is well known that IGZO can be used to make very efficient DRAM cells [5]. However, since the thin-film platform provides only n-type transistors, creating the readout for DRAM cells is not as easy as it might initially look.

Project objectives

In this internship you will characterize DRAM elements, and design scalable readout periphery which can interface with our microprocessor. We have already some first experimental DRAM cells and mini-arrays fabricated in PragmatIC’s IGZO technology. You will evaluate the performance of these cells and mini-arrays, such as the speed, retention time, power consumption, ... Depending on the length of the internship, we will then look into the design of the next generation of test circuits. If time allows, we also want to share the results in a publication.

Project tasks

As the intern, you will follow these steps:

  • Read up on the specifics of the IGZO technology and digital circuit design
  • Measure basic circuits with available lab equipment
  • Design PCBs for the measurements which cannot yet be done with available equipment, use them
  • Optional: use the learnings to design the next iteration of the memory
  • Optional: write a research paper on the findings

Requirements

To bring this project to a satisfying conclusion, you will need the following things:

  • A background in circuit design
    • Preferably enrolled in a circuit design master or adjacent
  • Enjoy getting your hands “dirty” in the lab
  • Strong communication skills
  • Lots of positive energy and initiative
  • The desire to be part of an enthusiastic and supportive team

Depending on the time available this internship can be anywhere from 3 to 9 months.

Further reading

[1] Multi-project wafers for flexible TF electronics by independent foundries, https://doi.org/10.1038/s41586-024-07306-2

[2] 3.55-Watt LTPS TFT DC-DC converter https://doi.org/10.1002/sdtp.16506

[3] Flex6502, https://doi.org/10.1109/ISSCC42614.2022.9731790

[4] Flexible RISC-V microprocessor, https://www.nature.com/articles/s41586-024-07976-y

[5] Capacitor-less, long-retention DRAM https://doi.org/10.1109/IEDM13553.2020.9371900



Type of project: Internship

Duration: 3 to 9 months (pending availability)

Required degree: Master of Engineering Technology, Master of Engineering Science, Master of Science

Required background: Electrotechnics/Electrical Engineering, Nanoscience & Nanotechnology, Other

Supervising scientist(s): For further information or for application, please contact: Florian De Roose (Florian.DeRoose@imec.be) and Hikmet Celiker (Hikmet.Celiker@imec.be)

Imec allowance will be provided for students studying at a non-Belgian university.

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