Achieving 3-dimensional high-resolution, quantitative tomography layer interfaces

The functionality and performance of advanced semiconductor devices is a tight interplay between the structure and chemical composition at the atomic level. The interfaces between different layers play also an important role in the physical properties of semiconductor devices as e.g. in strained layer superlattices, quantum dots, surface and buried channel field effect transistors…. Diffusion and crystalline defects at the interfaces can degrade the performance of the devices. It is therefore crucial to characterize at the nanoscale in 3 dimension (3D) these interfaces. Clearly, device fabrication and characterization, two processes that must go hand-in-hand, become increasingly complex and call for clever fabrication and 3D metrology solutions with close to atomic precision.

Two complementary microscopy techniques have emerged over the last years as key players for the nanoscale characterization : Transmission Electron Microscopy (TEM) and atom probe tomography (APT). While TEM/EDS offers superior spatial resolution and accuracy, elemental sensitivity is a bottleneck in the analysis of advanced nano-devices. On the other end, APT provides high elemental selectivity (from H to U) and sensitivity, but its quantitative and spatial accuracy is strongly degraded in systems containing different materials. Ultimately, the complementary (hybrid) use of both concepts shows great potential for 3D atomic-scale analysis as it would overcome these limitations. Albeit their analytical power, TEM/APT analysis of complex nanostructures suffers from numerous challenges (sample preparation, quantification, reconstruction), particularly for hybrid approaches, that need to be addressed to achieve the analytical precision and accuracy demanded by the industry.

This project will focus on the development needs for the interface 3D nanoscale characterization by TEM/APT in 5 nm node (and below) single devices. This will require:

a)      Learning FIB, TEM and APT methodologies relevant to future CMOS based memory and logic device fabrication.

b)     Evaluating and understanding the role of TEM/APT specimen thickness, associated ion beam damage and/or beam-driven dynamics on analysis results and analytical power (artefacts, spatial and quantification uncertainty, limitations, etc.).

c)      Developing analytical workflows, data processing and physics based analysis protocols (data correlation, de-noising, background correction, etc.) to enable high resolution, quantitative 3D hybrid metrology.

 

d)     Understanding the physics that lead to artifacts in the APT spatial reconstruction and optimizing the reconstruction procedures relying on TEM information.

Through this PhD, the successful applicant will interact with the integration, test, design, and analysis groups at imec in order to map out metrology process flows with optimization of TEM and APT insertion points being of primary interest. This could also include examination/development of hybrid approaches pulling in information from other metrology techniques.

To be eligible, applicant must have a master’s degree in either physics, nanoscience or chemistry, with a strong background in solid-state physics, material science and/or materials characterization. As the PhD will include a large amount of experimental work on complex systems, previous analytical experience and a basic knowledge of semiconductor process flows would be beneficial.