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Imec furthers high-mobility nanowire FETs for nodes beyond 5nm
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Silicon photonics technology for next-generation datacenter interconnects
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Solving the contact resistance challenge for 7nm and beyond CMOS
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Imec and partners report major breakthroughs for spintronic logic devices in two different implementations
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Imec demonstrates the feasibility of introducing SST-MRAM as a last-level cache at the 5nm technology node
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Imec first to stack FinFETS with 45nm fin pitch using sequential 3D integration
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Imec improves performance and understanding of stacked nanowire Gate-All-Around transistors for N3 and beyond
Published on:
19 June 2018
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