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Imec Extends Damascene Metallization Towards the 3nm Technology Node
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Silicon photonics technology for next-generation datacenter interconnects
How to efficiently cool power electronics and optoelectronic sensors?
Make smartphones and autonomous vehicles see the impossible
Solving the contact resistance challenge for 7nm and beyond CMOS
A cold shower for chips
Sensor searches demanding application
A 300mm platform for 2D-material based MOSFET devices
Iuliana Radu on quantum computers
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Imec improves performance and understanding of stacked nanowire Gate-All-Around transistors for N3 and beyond
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Imec first to stack FinFETS with 45nm fin pitch using sequential 3D integration
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Imec and partners report major breakthroughs for spintronic logic devices in two different implementations
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Imec demonstrates the feasibility of introducing SST-MRAM as a last-level cache at the 5nm technology node
Published on:
4 June 2018
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