alt

To Stories

imec logo

Imec and Cadence Tape Out Industry’s First 3nm Test Chip

Extreme ultraviolet and 193 immersion lithography technology and Cadence digital tools used to design 3nm CPU core

Reading room

alt
Silicon photonics technology for next-generation datacenter interconnects
alt
How to efficiently cool power electronics and optoelectronic sensors?
alt
Make smartphones and autonomous vehicles see the impossible
alt
Solving the contact resistance challenge for 7nm and beyond CMOS
alt
Sensor searches demanding application
alt
A cold shower for chips
alt
A 300mm platform for 2D-material based MOSFET devices
alt
Iuliana Radu on quantum computers
Cleanroom

Press

Imec first to stack FinFETS with 45nm fin pitch using sequential 3D integration
Man in white suit working in imec cleanroom

Press

Imec improves performance and understanding of stacked nanowire Gate-All-Around transistors for N3 and beyond
alt

Press

Imec and partners report major breakthroughs for spintronic logic devices in two different implementations
Man in white suit working in imec cleanroom

Press

Imec demonstrates the feasibility of introducing SST-MRAM as a last-level cache at the 5nm technology node

Published on:

28 February 2018

Contact us