Phononic-enhanced logic gate

As digital electronics push the boundaries of miniaturization and performance, improving power efficiency has become a critical challenge, especially in advanced computing architectures. Traditional silicon-based logic gates are increasingly limited by high power consumption and heat dissipation. To address these challenges, this research focuses on integrating piezoelectric materials and phononic features directly at the logic gate level, within emerging architectures such as Complementary FET (C-FET). This approach aims to revolutionize how logic gates process signals and use energy.

Piezoelectric materials possess the unique ability to convert mechanical stress into electrical energy, while phononic crystals can control the propagation of acoustic waves. By leveraging these properties, this research proposes to develop innovative logic gates that combine phononic and piezoelectric functionalities, enabling more energy-efficient switching and signal transmission. Unlike conventional approaches that focus on device-level enhancements, this study will apply these technologies directly to logic gate operations in advanced architectures like C-FET, which are poised to play a crucial role in future low-power computing systems.

The key objective of this PhD research is to design, simulate, and experimentally validate novel logic gates that use piezoelectric and phononic features to enhance power efficiency. This will involve creating computational models to explore how power transfer across physical domains can be used in logic functions, optimizing material properties and device geometries for maximum efficiency, and fabricating prototypes of these logic gates. The performance of these gates will be compared to that of traditional CMOS logic gates and tested for their suitability within emerging architectures like C-FET, with a focus on reducing energy consumption and improving performance at the nanoscale.