Multiscale Modeling of Stress Engineering in CFET Channels and Interaction with Local Interconnects

Background:

Complementary Field-Effect Transistor (CFET) technology represents a significant advancement in semiconductor devices, offering potential improvements in performance and scaling. Stress engineering in CFET channels and their interaction with local interconnects is a critical area of study to optimize device reliability and efficiency. Traditional modeling approaches often fall short in accurately predicting the complex stress distributions that arise from various sources, such as thermal-mechanical mismatch, lattice mismatch, and local heating due to Joule heating and high-frequency switching.

To address these challenges, this research proposes the development of a comprehensive multiscale modeling framework that integrates appropriate high fidelity models at appropriate length-scales and trains relevant surrogate models such that an efficient thermal-mechanical digital twin of CFET channels and local interconnects can be developed through multi-fidelity approaches, enabling accurate prediction of thermal-mechanical stresses, especially towards channel stress optimization and reliability evaluations. Such models should be trained to capture the properties of superlattices in CFETs. The digital twin will incorporate feedback from the fabrication process and integration data, ensuring that predictions are continuously refined and accurate. Uncertainties quantification approaches will be utilized to address the impact of unknown fabrication and process parameters.  

Additionally, by linking the digital twin with an actual fabricated CFET module, not only the study will obtain data on the fabrication history and but also from module test data, further enhancing the accuracy and reliability of the predictions.

Problem Statement:

The interaction between CFET channels and local interconnects introduces complex stress distributions that can significantly impact device performance. Current models lack the integration of multiscale approaches and feedback mechanisms to accurately predict these stresses. Furthermore, the computational costs associated with detailed simulations can be prohibitive, necessitating the development of efficient modeling techniques.

Objectives:

The primary objectives of this research are:

Develop a digital twin of CFET channels and local interconnects that incorporates feedback from the fabrication process and integration and test data. The digital twin will incorporate multi-scale and multi-fidelity approaches to minimize computational costs.
Accurately predict stress distributions arising from thermal-mechanical mismatch, lattice mismatch, and local heating.
Innovate CFET designs and technologies that leverage stress effects to enhance channel mobility and overall device performance.
 

Related reading:

[1] Wang, Y. Nanosheet-based complementary transistors with a 48 nm pitch. Nat Electron 6, 933–934 (2023). https://doi.org/10.1038/s41928-023-01090-z

[2] L. Jiang et al., "Complementary FET for Advanced Technology Nodes: Where Does It Stand?," 2021 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Dallas, TX, USA, 2021, pp. 11-14, doi: 10.1109/SISPAD54002.2021.9592562.

[3] https://semiengineering.com/building-cfets-with-monolithic-and-sequential-3d/

[4] https://semiengineering.com/introducing-nanosheets-into-complementary-field-effect-transistors-cfets/

[5]https://www.imec-int.com/en/articles/imec-puts-complementary-fet-cfet-logic-technology-roadmap

[6]https://www.imec-int.com/en/articles/towards-process-flow-monolithic-cfet-transistor-architectures

 
Required background: engineering science, engineering technology

Type of work: 10% literature and technological study, 60%  modelling and simulation, 30% to design and conduct experiments to calibrate and validate the computational models.

Supervisor: Houman Zahedmanesh

Daily advisor: Juergen Boemmels

The reference code for this position is 2025-050. Mention this reference code on your application form.