Driving the design of next generation of reconfigurable systems through technology innovations

State-of-the-art reconfigurable systems (FPGAs, CGRAs, etc.) suffer from nearly 10x performance penalty compared to ASIC-based systems. The performance penalty occurs primarily to enable bit-level reconfiguration in FPGAs. This reconfiguration enables the system to implement application-optimized designs on FPGA systems.  Further, the organization of the computation, memory and interconnect elements and the resulting integration also contributes to the reduced performance. Leveraging both device and integration technology innovations can result in reduced performance and resource penalty in such reconfigurable systems.

The student will be working on an exploration framework for evaluating such technology innovations in FPGA-like reconfigurable systems. The project will also involve driving technology innovations appropriate for reconfigurable systems, across computation, communication, and memory, to provide optimized PPAC (power, performance, area, and cost) trade-offs.

Type of work: 30% literature survey to gain an understanding of the landscape of technology innovations and state-of-the-art reconfigurable systems. 70% hands-on modelling and framework development for driving the technology-aware design and exploration of FPGA-based systems.