Configurable Logic Blocks for CMOS 2.0 FPGAs
PhD - Leuven | Just now
This PhD opportunity tries to tackle the design of reconfigurable architectures and building blocks by rethinking the reconfigurable logic using IMEC’s CMOS 2.0 concept with strong system/design and technology focus. You will work with IMEC’s advanced technology PDK suited for Angstrom nodes to design new generation of reconfigurable logic blocks, by designing reconfiguration memory, compute path, data path (FFs), control path, local/global MUX layers. You will demonstrate proof of concept for CMOS 2.0 configurable logic blocks and programmable interconnect using advanced technologies of IMEC to design both the netlist and layout, and be able to quantify Power Performance Area (PPA) and benchmark it against conventional 2D design.
During this PhD, you will collaborate with cross-functional teams starting from architecture experts to technologists and chip designers. Moreover, you will often interact with other PhD students working on related topic at different abstraction levels. You will specifically work with IMEC’s DTCO and STCO programs and hence gain insights and understanding of the scaling problem and the implications on reconfigurable systems at several abstraction layers (technology, circuit design, system design and workloads) leading to an impactful PhD.
More specifically, your work will involve the following activities:
Starting point: open-source FPGA fabric, possibly FABulous or OpenFPGA: Begin the research by exploring and utilizing an open-source FPGA fabric like FABulous or OpenFPGA. This will serve as the foundation for further design and experimentation.
Design MUX layers: Focus on designing multiplexer (MUX) layers, which are crucial for routing signals within the FPGA. This involves understanding the trade-offs between complexity, speed, and area.
Local vs global interconnection: Investigate the differences between local and global interconnects within the FPGA. Local interconnects are used for short-distance connections, while global interconnects handle longer distances and require different optimization strategies.
Logic (LUT) vs interconnect: Study the balance between logic elements, such as Look-Up Tables (LUTs), and interconnect resources. This involves analyzing how each component impacts the overall performance and efficiency of the FPGA.
Layer split with equal sizing: Explore the concept of splitting layers with equal sizing to optimize the FPGA's layout. This includes determining the best way to distribute logic and interconnect resources across different layers.
Logic vs interconnect density, type of logic, flexibility vs area of programmable interconnect, local vs global interconnect programmability: Delve into the trade-offs between logic density, interconnect density, and the type of logic used. Assess the flexibility of programmable interconnects and how local and global interconnect programmability affects the FPGA's performance.
Investigate runtime reconfiguration and multi-context: Research the potential of runtime reconfiguration and multi-context capabilities in FPGAs. This involves understanding how these features can enhance the adaptability and efficiency of the FPGA.
Runtime reconfiguration now becomes very efficient by context switching in bistable plane/layer: Examine how context switching in a bistable plane or layer can make runtime reconfiguration more efficient. This includes studying the mechanisms and benefits of this approach.
PPA quantification: Quantify the Performance, Power, and Area (PPA) metrics of the FPGA designs. This involves rigorous analysis and benchmarking to evaluate the effectiveness of different design choices
Required background: Electrical and electronics engineering
Type of work: 40% logic design, 40% physical design, 20% literature
Supervisor: Marian Verhelst
Co-supervisor: Mehdi Tahoori
Daily advisor: Siva Satyendra Sahoo
The reference code for this position is 2025-188. Mention this reference code on your application form.