Circuit Design for Optimized SOT-MRAM: Area, Latency, and Power

Proposed Outline of the Dissertation:

Spin-Orbit Torque Magnetic Random-Access Memory (SOT-MRAM) is emerging as a promising candidate for future memory technologies due to its non-volatility, high speed, and low power consumption. This PhD research aims to design and optimize SOT-MRAM circuits focusing on area, latency, and power. The study will involve the design and testing of a test chip for SOT-MRAM macros in various configurations, including baseline 2T1R, 1S1T1R, and multipillar configurations.

The dissertation will cover the following key areas:

1. State-of-the-Art Analysis:
• Review of current SOT-MRAM technologies and their applications.
• Comparative analysis of different MRAM configurations (2T1R, 1S1T1R, multipillar).
2. Analog Circuit Design:
• Development of read/write circuitry optimized for area, latency, and power.
• Design of test structures and macro control circuits.
3. Digital Circuit Design
• Implementation of Error Correction Code (ECC) and Built-In Self-Test (BIST) mechanisms among other support modules.
• Implementation of interfaces towards Processing Elements in a wider compute system.
4. Simulation and Modelling:
• Use of advanced simulation tools to model SOT-MRAM behavior.
• Evaluation of circuit performance through simulations at different abstraction level: array, bank, macro and system, by using a pure analog and AMS environment as required.
5. Test Chip Design and Fabrication:
• Design and layout of a test chip incorporating various SOT-MRAM configurations.
• Collaboration with fabrication facilities for chip manufacturing.
• Implementation of design for characterization (device level) and design for test (circuit/module level) capabilities.
6. Testing and Validation:
• Post-fabrication testing of the SOT-MRAM test chip.
• Analysis of test results to validate design choices and optimize performance.
7. Conclusion:
• Identification of key technological enablers and integration challenges.
• Recommendations for future research and development in SOT-MRAM circuitry.