Alleviating Thermal Challenges In Angstrom Nodes: Paving The Way For 3D Integrated Circuits (3D-ICs) of The Future

Semiconductor technology driven by Moore’s law has reached an inflection point due to physical and technological barriers. Further innovation is fueled by the disintegration of various functional components in an IC and subsequent re-integration using advanced packaging techniques like 2.5D and 3D system integration. The separate and tailored optimization and integration, also popularly known as heterogeneous integration (HI) allows for achieving higher performance per Watt of power. In this context, IMEC’s CMOS 2.0 paradigm1 views separate tiers for high drive logic, high-density logic, level 1 (L1) and level 2 (L2) caches (SRAMs), and power delivery network (PDN), clock delivery network (CDN) and I/Os.  

However, several challenges come in the way of this attractive option: among which thermal challenges are the foremost due to higher power density even if the 3D system could run at lower operating frequency than the 2D counterpart. Both electrical and thermal resistances are becoming prohibitively large for a functional 3D-IC package. However, the thermal profile of a 3D-IC could be controlled using careful system co-optimization techniques across the complete stack, starting from SoC system architecture configuration, through 3D-IC technology choice, 3D system partitioning, 3D floorplanning, package cross-section optimization, and up to cooling. While current state-of-the-art EDA tools enable to perform such holistic layout, power & thermal analysis, there is still a huge gap in the understanding how different trade-offs impact the 3D-IC Performance, Power, Area & Temperature (PPAT) analysis. 

This PhD opportunity tries to tackle the  thermal management challenge of ICs with a strong system/design and technology focus. You will work with IMEC’s advanced technology PDK suited for Angstrom nodes to lay out commercial design benchmarks executing realistic workloads. You will assess typical power density demands in these advanced technologies while running these workloads. You will develop an understanding of both the spatial and temporal dynamics of localized thermal hotspots and their interactions. Based on these findings, you will devise different thermal mitigation strategies to effectively take out the trapped heat in the stack, e.g. thermal material innovation or new design tricks (thermal-aware design) to keep the chip temperature under check. Finally, you will also evaluate the PPAT penalties incurred due to the introduction of these thermal mitigation techniques.   

During this PhD, you will collaborate with cross-functional teams starting from thermal experts to technologists and chip designers. Moreover, you will often interact with EDA vendors for tool support in your work. You will specifically work under IMEC’s DTCO and STCO programs and hence gain insights and understanding of the thermal problem and its management at several abstraction layers (technology, circuit design, system design and workloads) leading to an impactful PhD. 

More specifically, your work will involve the following activities: