Advanced thermal management of wafer-level optical interconnects in next-gen AI/ML systems

Over the past decade, Silicon Photonics (SiPho) has emerged as a key enabling technology for datacenter optical interconnectivity and is now considered to enable high-bandwidth optical interconnectivity networks in future high-performance computing (HPC) and machine learning (AI/ML) systems [1]. In the pursuit of minimizing interconnect parasitic losses, the optical transceiver is being integrated as close as possible to the host IC. With this in mind, the co-packaged optical module (CPO) was introduced (Fig.1, A), where the optical transceiver is integrated directly adjacent to the host IC on the same interposer substrate. Taking this one step further, 3D integration by die stacking of an active SiPho transceiver die on a host IC can be done. This highly integrated approach opens the opportunity for optically interconnecting multiple GPU/CPUs on an optical interposer wafer (Fig.1, B) [2]. Current optical I/O links based on SiPho technology are however significantly affected by changes in local and ambient temperature variations, e.g. caused by the highly non-uniform power generation in the host IC, the laser sources, and the optical devices themselves. This introduces thermal management challenges: high levels of thermal cross-talk between the host IC and transceiver are expected, which could detune optical resonance-based devices. Combining multiple high-power CPU/GPUs (>700 Watt) on an optical interposer wafer leads to a high thermal load of tens of kW which has to be removed with adequate active (liquid) cooling solutions.