Nokia Bell Labs, KU Leuven and imec work collaboratively on 5G SoC

The targeted realization of a zero-emission Radio Access Network (RAN) necessitates a drastic decrease in power consumption through increased energy efficiency as well as the greater use of renewable energy.

About 80% of a mobile network’s energy is consumed by base station sites. In particular, the composing chipsets. or systems-on-chips (SoC), are major contributors to the energy consumption. The base station systems for beyond 5G hence need to be highly energy efficient on the one hand, but on the other hand they also need to handle extremely high data rates, should not introduce high processing latency and provide sufficient flexibility for features like dynamic spectrum sharing. An impossible challenge? No.

In a tight collaboration with KU Leuven, Nokia Bell Labs has developed a novel stream processor SoC that consists of a 2D array of parallel processing elements, that are interconnected to neighboring elements and capable of processing a variety of physical layer algorithms with extremely low power consumption and latency. Actual chip measurement results show a peak energy efficiency of 357.4 giga-operations per second per watt, marking a phenomenal 2x improvement over state-of-the-art processors.

On-chip memory accesses are another major contributor to power consumption in SoCs. Together with imec, Nokia Bell Labs have developed a novel way to partition the SoC’s on-chip memory system and to drastically reduce the energy consumption. In order to achieve an optimal partitioned architecture, we have devised a simulation platform that allows a fast design-space exploration. Using this simulator, we have shown over 50% reduction in memory energy consumption for different applications.

Both above-mentioned technology breakthroughs are cornerstones in our journey to ultimately realizing a zero-emission RAN.