SPIE Advanced Lithography + Patterning

Imec at SPIE Advanced Lithography + Patterning 2023

This year at SPIE Advanced Lithography + Patterning, imec has a record number of 70 contributions, of which 42 first authored papers and 28 co-authored papers. These papers show imec’s progress in advanced patterning challenges, such as (High NA) EUV lithography, CFET patterning, DRAM patterning, and the supporting role of machine learning techniques. Next to that, imec is leveraging nanoimprint lithography for bioelectronic applications, and will be giving an invited talk about its progress.

With sustainability becoming an increasingly more important aspect for chip design and manufacturing, imec has initiated a project that looks into sustainable semiconductor manufacturing techniques for lithography and etch. Imec will introduce several solutions for reduction, recycling and recovery of various materials used in high-impact areas of these manufacturing techniques. Emily Gallagher, a principal member of the technical staff, will also be a panelist at the SPIE AL+P with a panel on “Sustainability and Lithography’s Role”.

Finally, imec will host one course on stochastic lithography, given by John S. Petersen, scientific director of Advanced Patterning.

Imec highlights

Having put complementary FET (CFET) on the logic technology roadmap, imec is now looking into the patterning challenges faced by the next generations of transistor architectures. The following selection of papers report progress on sequential and monolithic CFET patterning processes:

• Monolithic CFET patterning challenges for ultimate CMOS device scaling
  Naoto Horiguchi
  28 February 2023 • 1:30 PM - 2:00 PM
• Gate patterning development for monolithic CFET integration
  Emmanuel Dupuy, et al.
  28 February 2023 • 2:30 PM - 2:50 PM
• Challenges for spacer and source and drain cavity patterning in CFET devices
  Geert Mannaert, et al.
  1 March 2023 • 9:00 AM - 9:20 AM
• Middle-of-line plasma dry etch challenges for CFET integration
  Dunja Radisic, et al.
  1 March 2023 • 9:20 AM - 9:40 AM
• DTCO of sequential and monolithic CFET SRAM beyond A5 technology node
  Hsiao-Hsuan Liu, et al.
  1 March 2023 • 3:50 PM - 4:10 PM
• In-line metrology for vertical edge placement control of monolithic CFET using CD-SEM
  Wei Sun, et al.
  2 March 2023 • 2:30 PM - 2:50 PM

Read more about CFET in imec’s stories

Imec is preparing the High NA patterning ecosystem for the imec-ASML Joint High NA Lab, which will be centered around the first 0.55NA extreme ultraviolet (EUV) lithography prototype tool and will be key to advance Moore’s Law beyond 2nm technology generations. Progress is reported in developing patterning and etch processes, in screening new resist and underlayer materials, in improving metrology and photomask technologies, as presented in the following selection of papers:

• Feasibility of logic metal scaling with 0.55NA EUV single patterning
  Dongbo Xu, et al.
  1 March 2023 • 1:40 PM - 2:00 PM
• Scaled-down deposited underlayers for EUV lithography
  Mihir Gupta, et al.
  1 March 2023 • 5:30 PM - 7:00 PM
• Resolution enhancement techniques @0.55 NA EUV applied for 6th generation of 10nm DRAM
  Ana-Maria Armeanu, et al.
  27 February 2023 • 4:40 PM - 5:00 PM
• Continued optimization of point-of-use filtration in metal oxide photoresist to reduce defect density
  Tetsu Kohyama (Nihon Entegris G.K.), et al. / imec co-author
  27 February 2023 • 2:00 PM - 2:20 PM PST
• Mask absorber/tone and process impact on resist line-edge-roughness
  Laurence S. Melvin III (Synopsys), et al. / imec co-author
  1 March 2023 • 5:30 PM - 7:00 PM PST
• Development on main chain scission resists for High NA EUV lithography
  Akihide Shitori (Zeon Corp), et al. / imec co-author
  27 February 2023 • 11:50 AM - 12:10 PM PST
• Recent advances in EUV patterning in preparation towards High NA EUV
  Seiji Nagahara (Tokyo Electron Ltd.), et al. / imec co-author
  1 March 2023 • 5:30 PM - 7:00 PM PST
• Etch optimization for defect reduction of EUV photoresists
  Alexandra Krawicz (TEL Technology Ctr., America, LLC), et al. / imec co-author
  28 February 2023 • 3:40 PM - 4:00 PM PST

Imec leverages its partners in the semiconductor industry, material companies and fundamental research to develop innovative EUV pellicle design, used to protect the photomask from contamination during high-volume semiconductor manufacturing. After earlier announcing the first successful fabrication and scanner handling of full-field CNT-based pellicles, imec presents recent optimizations and results in following papers:

• CNT pellicles: Recent optimization and exposure results
  Joost Bekaert, et al.
  1 March 2023 • 8:00 AM - 8:20 AM
• EUV pellicle scanner integration for N2 nodes and beyond
  Mark A. van de Kerkhof, et al.
  1 March 2023 • 8:20 AM - 8:40 AM

As part of its Sustainable Semiconductor Technologies and Systems program, imec is looking into sustainable semiconductor manufacturing techniques for lithography and etch. Using a virtual lab at process level, imec identifies the highest impact areas to reduce the impact of both lithography and etch emissions associated with fabricating an N2 logic wafer.

• Sustainable semiconductor manufacturing: Lessons for lithography and etch
  Emily E. Gallagher
  2 March 2023 • 8:00 AM - 8:30 AM

Panel

• Sustainability and Lithography’s Role: A Panel Discussion
  28 February, 2023, 6:00PM-7:00 PM
  with Emily Gallagher, principal member of technical staff

Course

• Stochastic Lithography
  26 February, 2023, 8:30AM – 5:30PM
  with John S. Petersen, scientific director advanced patterning

Program

View all imec contributions here.

Event details

Attend and hear research, challenges, and breakthroughs as you gather with colleagues in San Jose
Join other leading researchers who are solving challenges in optical and EUV lithography, patterning technologies, metrology, and process integration for semiconductor manufacturing and adjacent applications.

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