PRiME 2024

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Epitaxial SiGe/Si Multi-Stacks: From Stacked Nano-Sheet to Fork-Sheet and CFET Devices - Roger Loo - 10h20-11h20

The scaling evolution from stacked nano-sheet devices to fork-sheet devices and CFET architectures went together with increased complexities of the epitaxial growth schemes. This is valid for both the Si/SiGe multi-layers which define the thickness of the nano-sheet channels as well as the vertical distance between individual nano-sheets and also for the epitaxially grown source/drain (SD) layers which require a continuous increase in active doping concentration and a reduction in thermal budget without compromising material quality.

Fork-sheet transistors are lateral nano-sheet devices with a forked gate structure [1,2]. The physical separation of n- and p-devices by a dielectric wall enables device scaling and, consequently, sheet width maximization within the limited footprint of low-track-height standard cells. Bottom dielectric isolation has been proposed to circumvent the junction isolation trade-off between punch-through suppression on the one hand and junction leakage and capacitance on the other hand [3]. A typical fabrication scheme includes the challenging epitaxial growth of fully strained Si/Si_1-yGe_y/multi-{Si_1-xGe_x/Si} epi stacks (y>x) where the bottom Ge-rich Si_1-yGe_y layer is later replaced by a SiN/SiCO isolation [4,5].

In the CFET architecture, n- and p-MOS devices are placed on top of each other, thus completely removing the area consumption by the n-p spacing. This allows for further maximizing the effective channel width and, hence, the drive current [6-9]. The architecture can be fabricated following either a monolithic or a sequential approach. In the first option, n- and p-MOS transistors are built on the same wafer, while the sequential fabrication flow is based on wafer-to-wafer bonding techniques. The strengths and challenges of both approaches are discussed in [9]. In the monolithic approach, device fabrication starts with the epitaxial growth of an even more complicated Si/SiGe multi-stack with two different Ge concentrations (Fig. 1) [10], and where Ge-rich Si_1-yGe_y layers are later replaced by isolating dielectrics [9]. Owing to the very small dimensions (e.g., sub-10 nm nano-sheet channel width), high etching selectivity of the Si_1-yGe_y layers towards both Si_1-xGe_x and Si, and excellent process controls are mandatory. This sets stringent requirements on the epitaxial layer stacks (thicknesses and composition control, sharpness of interfaces, and absence of strain relaxation) [4,5,10,11] as well as on the Si_1-yGe_y etch process (high selectivity, limited consumption of Si_1-xGe_x and Si) [11-14].

To alleviate scaling-related contact issues in these devices, high performance metal / SD junctions are key [15]. Selective epitaxial growth (SEG) processes yielding heavy active doping are therefore required (Fig. 2), in addition to introducing innovative contact materials and designs [16-18]. The resulting electrical performance is, however, restricted by doping solubility limits and loading effects (impact of substrate patterning) inherent to scaling. Those must be circumvented to enable the upcoming generations of components. Moreover, novel device architectures add stringent constraints regarding pre-epi cleaning strategies, thermal budgets, and stability [19].

This work describes the material requirements of the different layers and the progress made on the associated epitaxial growth techniques.

Electrochemically Induced Templated Sol-Gel Deposition of Mesoporous Silica and Nanocomposite Thin Films - Vanheusden Genis - October 8th - 12h-12h20

Electrochemically induced sol-gel depositions have recently been gaining scientific interest for their ability to synthesize highly ordered mesoporous silica thin films on electrode substrates.¹ The process works by using cathodic reactions to electrogenerate OH^- ions through the reduction of a pro-base (e.g., water) and form an alkaline diffusion layer near the electrode surface. Within this alkaline zone, the gelation reactions of a pre-hydrolyzed, kinetically-inhibited silica sol-gel precursor solution are catalyzed, thus triggering the growth of a gel film onto the electrode. The addition of surfactant templates allows for the formation of mesoporous thin films with highly organized pore structures that have a wide range of applications in a wide range of fields. The advantages of this electrochemically induced process include the ability to control the deposition using electrochemical parameters, the faster gelation compared to conventional sol-gel, the option to omit high-temperature treatment/solidification steps and the ability to coat 3D structured electrodes. Furthermore, the rapid gelation is limited to the zone within the alkaline diffusion layer during film growth. Recently, we demonstrated improved process control by tuning the diffusion layer thickness using rotating disk electrodes², thereby inhibiting the formation of aggregated particle byproducts, and provided an in-depth overview of the mechanism and relevant aspects of the film growth³.

In the present work, the same electrochemically induced sol-gel process is performed using an ionic liquid as the template, leading to the controlled deposition of a functional ionic-liquid-templated silica gel layer that can be dried to an ionically conductive nanocomposite with applications for sensors, supercapacitors and solid-state Li-ion batteries. The nanocomposite under study is based on recent works wherein a Li-ion ionic liquid electrolyte (ILE) was nanoconfined in an inert silica matrix, synthesized via sol-gel reactions.^4–6 The nanoconfinement of the ILE in the mesoporous silica matrix results in a monolithic solid structure, while the Li⁺-ions retain liquid-like high ionic conductivities exceeding that of a pure ILE when the ion diffusion along silica wall/ILE interface dominates.^4,6 The conventional sol-gel process used to synthesize the ionic liquid-templated silica requires several days to solidify into the product. By using the electrochemically induced sol-gel process, we demonstrated the ability to controllably grow coatings of 1 to 35 micrometers thickness on electrode surfaces in mere seconds to minutes. The obtained films show comparable properties as films prepared through conventional gelation.

This presentation starts from an overview of the electrochemically induced sol-gel process for mesoporous silica thin films and outlines the methodology used to electrodeposit ionic-liquid-templated silica nanocomposite coatings. The functionality of the coatings as thin-film electrolyte was demonstrated in all-solid-state thin-film test-cells using TiO₂, LiMnO₂ (LMO) and LiNi_0.5Mn_1.5O₄ (LNMO) as cathodes with Li metal as the anode. Since these thin-film model systems allowed the formation of single, well-defined interfaces between the different components, the underlying electrochemical processes during charge-discharge cycles could be carefully monitored. In this way, this work demonstrates the flexibility of the electrochemically induced sol-gel process by extending the methodology to grow composite coatings, in this case useful for thin-film solid-state batteries.

Metallization for Advanced Semiconductor Technology Nodes: Wet-Chemical Deposition and Etching, Characterization, and (Semi) Damascene Approaches - Harold Philipsen - October 10th - 10h-10h40

To ensure semiconductor technology scaling to continue for the decades to come, the industry focuses on identifying alternative metals (elemental or alloys), that can replace copper in the back end of line (BEOL) integration scheme, for which the metal is used as main conductor for most of the metallization levels. Recently, the semi-damascene process is being developed, in which the interconnect metal is first deposited and then patterned using a dry etching process (‘direct metal etch’), in a fashion closely resembling the traditional Al metallization. One of the advantages is that any metal that can be deposited as a blanket thin film (either by physical vapor deposition (PVD), electrochemical deposition (ECD), electroless deposition (ELD), chemical vapour deposition (CVD), or atomic layer deposition (ALD)) can subsequently be patterned, provided that the critical requirement for dry etching of ‘volatilization’ of the metal is fulfilled. Furthermore, it allows the integration of materials for which no ECD, ELD, CVD or ALD process is available to fill damascene trenches.

In this contribution, intrinsic material properties (bulk resistivity, electromigration, ...) and composition (surface versus bulk composition as well as surface oxide) of a wide range of metals and alloys of interest to the BEOL will be compared. An overview of wet-chemical deposition approaches of a few selected metals (Cu and Rh) will be given. For ELD, the focus will be on discussing the mechanistic understanding of the intrinsically complex process, for which the stability and reactivity of the reducing agent is affected by solution pH and composition as well as the presence of oxygen. For ECD, results will be discussed for Rh and Ni, for which an electrochemical quartz crystal microbalance (EQCM) was used to quantify the amount of material deposited and interpret the various features detected in cyclic voltammograms. Metal ion solution speciation as well as stability, of importance for both deposition methods, has been studied using UV-vis spectroscopy and electrochemical characterization (linear sweep and cyclic voltammetry). Deposits were analysed morphologically using transmission electron microscopy and the chemical composition was assessed by elemental mapping.

During process integration, the surface-chemical composition of metals / alloys needs to be carefully controlled, as this can, for instance, critically impact metal line resistance or result in wet etching or corrosion. A few example cases in which this is relevant will be presented, e.g. the reversible surface oxidation and reduction of Cu was studied using EQCM, the surface chemistry of NiAl was characterized using electrochemical measurements, and the reversible surface nitridation of a model metal (Mo) is demonstrated as a method to protect against unwanted metal dissolution.

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Since 1987, this joint Pacific Rim international meeting of The Electrochemical Society (ECS), The Electrochemical Society of Japan (ECSJ), and The Korean Electrochemical Society (KECS) has been one of the world’s preeminent meetings on electrochemical and solid state science, and the organizers of PRiME 2024 are pleased to welcome everyone back to Honolulu, HI for this, the ninth gathering of the PRiME!

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