2025 Symposium on VLSI Technology and Circuits

Imec

Imec will showcase 16 contributions at the 2025 Symposium on VLSI Technology and Circuits, including 15 first-authored papers. These papers highlight advancements in various areas such as radar sensing, high-speed memory, ultra-fast DACs, hybrid bonding for interconnects, nerve stimulation ASICs, power delivery in 2nm CMOS, wideband digital PLLs, CFET integration, high-power GaN devices, 3D organoid interfacing, selective deposition for interconnects, fine-tunable gate stacks, 3D DRAM processes, GAA technology for the A10 node, and SRAM scaling using CFET architecture.

Imec is also hosting a short course on heterogeneous system partitioning, led by Senior Fellow Eric Beyne, on June 9 at 10:45.

Overview of imec contributions

Short courses

Short course 1: Key VLSI Technologies in the AI Era

• "Heterogenous System Partitioning, the 2.5D and 3D Integration Landscape and Roadmap", by E. Beyne, imec 

Papers

Circuits Session 2: RF/mm-wave Tx and Rx

• "An IEEE802.15.4ab/a/z Compatible IR-UWB 2TRX with Dual-Antenna Full-Duplex 1x3 SIMO Radar Sensing and Aliasing Suppressing Semi-Synchronous TX", A. N. Bhat, E. Allebes, E. Bechthum, Z. Xu, J. van Den Heuvel, P. van Zeijl, P. Mateman, S. van der Ven, M. Eskiyerli, S. Traferro, M. El Soussi, A. Farsaei, E. Tiurin, M. Zhou and S. Gamage, imec, Netherlands

Technology Session 4: RRAm and MRAM

• "High Density, High Speed STT-MRAM N7 Macros: Material and DTCO Exploration", D. Narducci, imec, Belgium

Circuits Session 12: Ultra High-speed Wireline

• "A 7-bit 150-GSa/s DAC in 5nm FinFET CMOS, B. Moeneclaey", J. Lambrecht, A. Parisi, J. Van Kerrebrouck, G. Coudyzer, A. Kankuppe, E. Martens, J. Craninckx and P. Ossieur, imec, Belgium

Technology Session 6: Technology Highlights 2 

• "High-Density Wafer Level Connectivity Using Frontside Hybrid Bonding at 250nm Pitch and Backside Through Dielectric Vias at 120nm Pitch After Extreme Wafer Thinning", L. Witters*, S. Van Huylenbroeck*, S. Kang*, P. Zhao*, S.-A. Chew*, K. D’havé*, S. Iacovo*, M. Stucchi*, B. Zhang*, S. Dewilde*, D. Montero*, R. Chukka*, K. Vandersmissen*, N. Heylen* and N. Jourdan*, *imec, Belgium **ASM International, Belgium and ***ASM International, Finland

Circuits Session 15: Biomedical Readout and Stimulation

• "A Flexible HV Stimulator ASIC with Stimulus-Synchronized Charge Balancing and Embedded CM Regulation for Implantable Peripheral Nerve Stimulation", M. Zhou*, H. Xin*, R. van Wegberg*, G. Langereis*, C. M. Lopez**, M. Konijnenburg* and N. Van Helleputte**, *imec, Netherlands and **imec, Belgium

Technology Session 7: 3D Power Delivery Network

• "Backside Power Delivery for Power Switched Designs in 2nm CMOS: IR Drop and Block-level Power-Performance-Area Benefits", Y. Zhou*, P. Venugopal*, L. Verschueren*, J. Cousins*, M. Brunion*, J.-Y. Lin*, H. Kukner*, M. Naeim**, M. Stassar*, **, A. Farokhnejad*, O. Zografos*, M. G. Bardon*, J. Myers*, J. Ryackaert* and G. Hellings*, *imec, Belgium and **Cadence Design Systems, Inc., USA

Circuits Session 19: Frequency Generation

• "A 2.3-15.8-GHz 8-Phase Injection-Ripple-Filtered Multi-Ring-Coupled DCO Enabling a Wideband Digital PLL", Z. Xu*, E. Allebes*, P. Mateman*, J. van den Heuvel*, S. van der Ven*, S. Traferro*, A. Kumar*, R. Li*, S. Nagata**, K. Bunsen**, T. Matsumoto** and M. Konijnenburg*, *imec, Netherlands and **Sony Semiconductor Solutions Corp., Japan

Technology Session 10: Advanced CMOS Platform

• "Monolithic CFET Flow Improvements Integrating Cover Spacer and Dual-WF RMG", C. Cavalcante, S. Demuynck, C. Sheng, D. Batuk, M. Hosseini, A. Peng, K. Stiers, A. Vandooren, H. Mertens, T. Chiarella, H. Arimura, J. Mitard, V. Georgieva, H. Puliyalil and A. Sepulveda Marquez, imec, Belgium

Technology Session 13: Power Devices

• "High Power/PAE (27.8dBm/66%) Emode GaN-on-Si MOSHEMTs for 5V FR3 UE Applications", A. Alian*, S. Yadav*, R. ElKashlan*, A. Sibaja-Hernandez*, H. Yu*, S. Banerjee*, B. O'Sullivan*, B. Kazemi Esfeh*, U. Peralagu*, B. Parvais*, ** and N. Collaert*, **, *imec and **Vrije Universiteit Brussel, Belgium

Circuits Session 24: Circuit Techniques for Biomedical Applications 

• "An Active Silicon Perforated MEA for Seamless 3D Organoid Interfacing with Low-Noise, Scalable Multimodal Electrophysiology", A. Rivero-Cortazar*, **, J. Aymerich*, S. Faizan Shaikh*, A. Lodi*, B. Raducanu*, G. Gielen*, ** and C. Mora 
  Lopez*, *imec and **KU Leuven, Belgium

Technology Session 18: Interconnects

• "Selective Deposition and Ruthenium Superfill Exploration Beyond A10 Node Interconnects", M. van der Veen*, G. Pattanaik**, T. Hakamata**, Y. Otsuki**, A. Romo Negreira**, J. Mayersky**, K. Yu**, R. Yonezawa**, H. Suzuki**, R. Clark**, A. Kumar Mandal*, A. Farokhnejad*, N. Jourdan*, P. Marien* and G. Murdoch*, *imec, Belgium and **Tokyo Electron Ltd., Japan

Technology Session 19: Gate Stack and BEOL Transistor Processes

• "Shifter materials and Stack Explorations for Vt Fine-Tunable Dual Dipole Multi-Vt Gate Stacks Compatible with Low Thermal Budget CFET", H. Arimura, L. Lukose, J. Ganguly, J. Franco, H. Mertens, J. Stiers, J.-G. Lai, A. N. Mehta, M. Bejide, M.-S. Kim and N. Horiguchi, imec, Belgium 

Technology Session 20: DRAM

• "Process Insights into 3D DRAM with Vertical Bit Line and Scalable GAA Transisto"r, N. Rassoul*, L. A. Labbate*, G. Eneman*, A. Fantini*, R. Ritzenthaler*, J. L. Prado*, R. Loo**, W. Devulder*, E. Dupuy*, T. Peissker*, A. Pacco*, H. K. Raut*, P. Eyben*, E. Canga* and E. Rosseel*, *imec and **Ghent Univ., Belgium

Technology Session 22: DTCO and Design Enablement 

• "Extending the Gate-All-Around (GAA) era to the A10 node: Outer Wall Forksheet Enabling Full Channel Strain and Superior Gate Control", L. Verschueren*, G. Eneman*, S. Yang*, J. Boemmels*, P. Matagne*, K. Beltran Cahuenas*, **, A. Sharma*, D. Abdi*, H. Mertens*, G. Mirabelli*, *** and G. Hellings*, *imec, Belgium, **Universidad San Francisco de Quito USFQ, Ecuador and ***Synopsys, Inc., Belgium
• "SRAM Scaling Opportunities Below 0.01 μm2 Using Double-Row CFET Architecture with Wordline-Folded Bitcell Design for Performance Optimization", D. B. Abdi, G. Hellings, J. Boemmels, F. Garcia-Redondo, L. Verschueren, A. Sharma, H. Kukner, M. Garcia-Bardon and J. Ryckaert, imec, Belgium

Event details

The IEEE Symposium on VLSI Technology and Circuits is one of the premiere technical conferences for semiconductor microelectronics, delivering a unique convergence of technology and circuits for the microelectronics industry as a fully merged event to maximize the synergy across both domains.

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